1. Field of the Invention
The present invention relates generally to computer systems architecture, and, more particularly, to a method and apparatus for stopping a bus clock for a point-to-point bus while no activity is present on such bus.
2. Description of the Related Art
Traditionally, the generation of graphics on computer systems have been accomplished via graphics devices coupled by a peripheral component interface (PCI) bus. Turning to the drawings, and specifically referring to FIG. 1, a conventional system 100 for generating such graphics on a computer display via a PCI 105 bus is shown. The system 100 includes a central processing unit (CPU) 110 for running a particular computer program thereon, with the computer program providing instructions to a graphics controller 120 to display such graphics on a display device (not shown). The PCI bus 105 is also coupled to a core logic 130, which is coupled to a main memory 140. The core logic 130 is a chipset that controls access to the main memory 140 by the graphics controller 120 for generating the graphics. The PCI bus 105 typically also couples other devices to the CPU 110, such as, for example, a disk drive 150.
The graphics controller 120 uses the main memory 140 to perform various graphics-related tasks, such as, for example, three-dimensional geometric calculations, accessing texture maps stored within the memory 140 for rendering 3D graphics, etc. The PCI bus 105 typically runs at 33 MHz, which permits a maximum transfer rate of 133 Mbyte/s between the graphics controller 120 and the main memory 140 to perform these various graphics-related tasks.
The PCI bus 105 is generally an adequate medium for interaction between the graphics controller 120 and core logic 130 to process basic two and three-dimensional graphics. However, with the significant increase in the sophistication of these graphics over the past few years, namely the emergence of complex three-dimensional graphics, the use of the PCI bus 105 for graphics applications has become problematical. As the graphics have become more complex, the graphics controller 120 requires greater, and quicker access, to the main memory 140 to process these complex tasks. The limited bandwidth of the PCI bus 105 limits the capability of the graphics controller 120 to efficiently generate these complex 3D graphics. Moreover, the graphics controller 120 shares the PCI bus 105 with other "non-graphics" related devices, such as the disk drive 150, thereby further reducing the amount of bandwidth the PCI bus 105 provides to the graphics controller 120. As a result, the PCI bus 105 has become more and more sluggish to adequately handle the latest in 3D graphics technology.
To alleviate the problems associated with the limited bandwidth available to the graphics controller 120 by the PCI bus 105, another technology, referred to as the "Accelerated Graphics Port" or "AGP", had been developed. In accordance with the AGP architecture, the graphics controller 120 is linked directly to the core logic 130 via an AGP bus 115, which runs at twice the speed of the PCI bus 105. As a result of its increased speed, the AGP bus 115 provides a minimum transfer rate that significantly dwarfs the transfer rate of the PCI bus 105. Moreover, the AGP bus 115 is a dedicated "point-to-point" bus, which provides direct access to the core logic 130 from the graphics controller 120. This provides a significant advantage over the PCI bus 105, in which the graphics controller 120 has to share the PCI bus 105 with other "non-graphics" devices.
With its increased transfer rate and direct "point-to-point" connection, the AGP bus 115 sufficiently handles the complex three-dimensional graphics of today's computer applications. However, as a result of the significant increase in speed that the AGP bus 115 provides over the PCI bus 105, the AGP bus 115 consumes significantly more power than the PCI bus 105. This drawback of the AGP bus 115 is particularly disadvantageous to portable or mobile computer users since it typically can drain the battery of a portable or laptop computer at a much quicker rate than the conventional PCI bus 105 for generating graphics.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.